At the end of the day, here's what it boils down to:
- you have to learn to use another tool (Modelsim) and all it's peculiarities and special incantations
- you can no longer simulate ahdl or mixed vhdl / verilog designs behaviorally
- there is a bigger "fixed cost" with making any design, as you have to build a test bench.
- This is a killer in small designs, but definitely saves time in bigger designs, as the modelsim simulator runs a lot faster and has some clever debug capabilities (that take time to learn). Also, when doing things like bus-based designs, these languages allow you to create procedures or tasks to do bus-writes or bus-reads, which allows you to set up PLD-based peripherals and registers a lot faster.
My guess from all this is that AHDL is going to disappear. VHDL and Verilog are very different languages from AHDL, and are, sadly,
significantly more verbose. I've been making the transition from AHDL to Verilog and now to VHDL for the last two to three years and it has been challenging.
I do moderate complexity PLD designs in support of PCB design, so I do a burst of PLD design activity for a while, then very little for months at a time. Whereas AHDL is a very literal text description of hardware, well written VHDL or Verilog is not. If you're used to laying out literal hardware blocks in your head - like I was - it will take you a while to make the paradigm shift to these languages.
The real catch is that each of these languages is actually TWO languages: a behavioral/simulation language and a hardware-description language. I'm OK with the hardware design side, but still haven't quite gotten all the subtleties of creating clean and transportable test benches.
It does seem like Altera is abandoning the low-end of PLD design in favor of supporting large customers doing large team-based designs. An end of an era.
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