Honored Contributor
Honored ContributorA few things of note:
1) The entire GUI was basically re-written in Q10.0. So it wasn't like the simulator's existing code was dropped. Instead it was decided to not spend a lot of time re-building this GUI-intensive feature. 2) Being an internal simulator, every model is custom built, i.e. it's not an HDL simulator(which is what you like about it). Each generation of devices has new/changing features, DLLs and DQS strobes for DDR, dedicated SERDES with DPA and CDR, transceivers, hard PCI Express cores, etc. These are hard enough to maintain for VHDL/Verilog simulators, but to throw in another hand-built model and verify is not a simple task. I'm guessing that's one of the major reasons. And you could argue that they should just not use this simulator for the high-end stuff, but all these high-end features are trickling down to the low end devices. Cyclone with high-speed transceivers, for example. I liked the simulator quite a bit too, for the reason of being able to simulate some small piece of code in about 2 minutes. As soon as something got more complex than that(and they often do), I regret having started down that path. I wish item 1) weren't an issue, in which case the simulator could have been left as is, and slowly die as it didn't support new features. I'm sure Altera is fully aware this allows designers who would have been 100% faithful to Altera tools to now look around. I think my only point is that it's a lot more complicated than they just dropped a feature for the heck of it, not that anyone said that's what happened...
