Altera feature downgrades w/ 10.x

I think that Altera, dismissing proprietary simulator and timing analyzer and completely adhering to Modelsim simulation, Synopsis design Constraint and TimeQuest Analyzer, allows the designers to move easily towards other FPGA vendors.

This is indeed a good point for us.

Further, this is a proof that Altera feels that their devices have equal (if not better) price/performance ratio with respect to the competitors.

Maybe difficult to slightly change our design habits at the beginning. But I think that at the end we'll get better devices and greater design flexibility.

IMHO.