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"poof"...really? Altera's been making people aware that this is going away for years now. All your other points (some quite valid) aside, surprise should certainly not be one of your sentiments.
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Uh huh, like I have nothing better to do than keep up with Altera press releases and their slow frog boil.
Like other HW engineers who do more than "code monkey" design, my CPLD/FPGA design load may vary between 0% and 100% on an inconsistent basis, depending on client needs and my design judgment. I might go months/years without using a tool, so when, as with Quartus 10.x, I revisit it several versions later than the last time, the cumulative deltas become quite apparent.
So I'll hold onto my reaction (disgust, now), thanks, and maintain my conclusion that Altera Quartus II v10.x has been castrated, downgraded, stripped of valuable and valued resources and features, and repositioned as just another d*ckwad HDL suite, suitable only for postmodern code-primates who evidently believe that anything non-Verilog lies in the realm of Stone Knives and Bearskins, and to whom Markus looks like hieroglyphics. So sad. Eye, emm, oh.
Guess I'll go fire up PALASM and maybe that newfangled ABEL. ;)
Honored Contributor
