Honored Contributor
Honored ContributorASIC design practices (using HDL coupled with SDC timing constraints) must be used on the high end of Altera's offerings and, I'd gather, that this is what drives them throughout their tools.
As to whether or not the issues you're all presenting are real, they are...but...they're not "just" Altera's issues. IMHO, the entire EDA industry has not really had any significant innovation (http://www.sigasi.com/content/latest-eda-innovation-logic-synthesis) since logic synthesis in the early 90s. Incidentally, the author is the creator of a nice little HDL tool called myhdl (http://www.myhdl.org/) (Python-based HDL) and his 'blog (http://www.sigasi.com/janhdl) always makes for interesting reading. Regards, slacker
