Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

ALTDDIO_OUT error 15874

Hi, I don`t know if this is the right forum for creating this thread.

I have a problem when I use the ALTDDIO_OUT IP component in Quartus II, for a Cyclone V device. I want to use the same output pin for two input pins. I have a selector that tells you if you want to route one input pin or another to that output pin.

In my case, I have two input ports: gb_A_tx_data and br1A_Rx_data. One of these inputs -gb_A_tx_data- comes from the ALTDDIO_OUT module, from its dataout output signal, like this

ddr_pin_out_gb_A : DDR_PIN_OUT

port map (

aclr => reset,

datain_h => ddr_out_gb_A_high,

datain_l => ddr_out_gb_A_low,

outclock => clk125,

dataout => gb_A_tx_data

); .

To select which port is going to the output port, I have done this:

gb_A_tx_d <= gb_A_tx_data when fpga_mode /= "00" else br1A_Rx_data;

The purpose of my device is to select which signal I want to connect to the output pin gb_A_tx_d. When I make that case, I receive this error:

Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|altddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto_generated|ddio_outa[4]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.

Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|altddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto_generated|ddio_outa[3]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.

Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|altddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto_generated|ddio_outa[2]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.

Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|altddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto_generated|ddio_outa[1]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.

If I don`t make the case and I connect directly the dataout to the output pin, I don`t receive the error. I mean, if I make gb_A_tx_d <= gb_A_tx_data I don't have any problem.

I understand that the ALTDDIO_OUT must be connected to the output pin directly. But, how can I get my purpose? Is that possible?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    the ddr output is meant for external output only (not inside fpga). you can mux your high/low inputs into ddr instead

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    the ddr output is meant for external output only (not inside fpga). you can mux your high/low inputs into ddr instead

    --- Quote End ---

    The problem is that I have to use the same output pin for two signals. I mean, I want to mux the output, not the input. If I mux high/low I will have the same problem in the output pin. Or maybe I have not understood your proposal.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    The problem is that I have to use the same output pin for two signals. I mean, I want to mux the output, not the input. If I mux high/low I will have the same problem in the output pin. Or maybe I have not understood your proposal.

    --- Quote End ---

    No you wouldn't. you can mux before ddr as many signals as you wish.