What device? Go to the handbook and into the Clock Network -> Clock Control Block section, and there should be a picture. There are two muxes into the global, one that is static based on configuration bits(although this one has the most flexibility) and one that is dynamic. So for Arria 10, the dynamic one can only switch between PLL outputs. For Cylone V, it's PLL outputs and one dedicated clock input pin. I don't think any of the dynamic inputs can be driven by a global(which is how another altclkctrl would feed into it).