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Lorne_K_Intel's avatar
Lorne_K_Intel
Icon for New Contributor rankNew Contributor
5 years ago

alt_ehip3_0 example design fails load alt_ehipc3_0 toolkit

Generate example design with

active channels : 10/29GE channels

single channel

RSFEC enabled : first_lane3,

ANLR enabled

example design : design completes build , fails to load

Oct 15, 2020 9:12:48 PM com.altera.systemconsole.unifiedtoolkit.InstanceLogger receiveMessage
SEVERE: An error occurred while running script "init_toolkit
": av_top_jtag_master: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.
while executing
"master_read_32 $master_claim_path $byte_address 1"
(procedure "reg_read" line 28)
invoked from within
"reg_read $base_addr $base_kr_ctrl"
(procedure "common_driver_pkg::read_fec" line 14)
invoked from within
"common_driver_pkg::read_fec"
(procedure "refresh_gui" line 44)
invoked from within
"refresh_gui"
(procedure "init_toolkit" line 18)
invoked from within
"init_toolkit"

2 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Can you share more detail so that I can debug and duplicate your issue in house


    1. May I know which Quartus version that you used ?
    2. Which FPGA product that you used ? Can you share with me the Ethernet IP QSYS file or IP file ?
    3. Which Intel dev kit board that you used ? Did you configured the dev kit board on board switch setting correctly ?
    4. Can you elaborate further on the procedure steps on how you run the software tool ? Which software tool to be precise here ?


    Thanks.


    Regards,

    dlim


  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    I am closing this case since I have not hear back from you for close to one month.


    Regards,

    dlim