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Lorne_K_Intel's avatar
Lorne_K_Intel
Icon for New Contributor rankNew Contributor
5 years ago

alt_ehip3_0 example design fails load alt_ehipc3_0 toolkit

Generate example design with active channels : 10/29GE channels single channel RSFEC enabled : first_lane3, ANLR enabled example design : design completes build , fails to load Oct 15, ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Can you share more detail so that I can debug and duplicate your issue in house


  1. May I know which Quartus version that you used ?
  2. Which FPGA product that you used ? Can you share with me the Ethernet IP QSYS file or IP file ?
  3. Which Intel dev kit board that you used ? Did you configured the dev kit board on board switch setting correctly ?
  4. Can you elaborate further on the procedure steps on how you run the software tool ? Which software tool to be precise here ?


Thanks.


Regards,

dlim