Honored ContributorHello everyone,
I am new with FPGA. Now I would like to learn FPGA but confused with AHDL, VHDL and Verilog. Could anyone describe what are the difference between them? What is your suggestion for me who want to start with FPGA? I find out that Verilog is a new one! Your replies are fully appreciated!
Honored ContributorAHDL is Altera HDL. Altera is a profit making company that keeps us going as well and runs this forum. They are very good people, believe me except for some of their documentations.
Verilog and vhdl are standardised by IEEE I believe. VHDL is commonly used in Europe but Americans like Verilog more just to be different. So pick your own.Honored ContributorAHDL is Altera's proprietary language. I would not bother to learn it.
VHDL and Verilog are the primary HDL languages. Learn a little bit about both and use the one you are most comfortable with. A lot of the newer Altera IP and verification IP is being delivered in SystemVerilog format (the newer-better-Verilog). I primarily develop with VHDL, but for designs that use Qsys and SOPC Builder I have been using SystemVerilog (to save fighting too much with the Altera Verification IP suite). Cheers, DaveHonored ContributorJust to give you the flavour:
VHDL is very tough on type and syntax. Hardly ever I wrote a program(12 years now) without failing first to many syntax errors. Verilog is more friendly, you can write anything and it is always happy.Honored ContributorAHDL is proprietory and is not supported by anything other than quartus, so no simulation is possible.
VHDL is strongly typed, so many problems can be picked up at compile stage and linting is not really required, but some people seem to find it tough to learn. Verilog is more C-like, and allows you to get away with more, but can lead to some more annoying debugging.Honored ContributorVHDL was developed for military purpose. more structured, and verbose.
I think you can be more creative with Verilog. I would recommend Verilog.Honored ContributorIf I were starting out today, I would use SystemVerilog. Altera has very strong support for it and is improving it with every release, and as someone mentioned, is developing new IP in this language. It is a super-set of Verilog and adds a lot of the structure that VHDL has, but it is optional to use it. IMHO, this is the way of the future of HDL (although we may never be able to fully kill VHDL unfortunately :-)
Honored ContributorThank you so much guys.
Now after read your replies, I think I will learn Verilog!Honored ContributorFYI, there is a new language in development called Bluespec. My question to others: What are the chances of this language becoming as popular/widely used as Verilog.
Honored ContributorI doubt it will have much of an impact, or at least it will take a while to dislodge VHDL or Verilog, as they have such large momentum.
We've had SystemC come along and there are companies that can claim synthesis of systemC, but it hasnt got much traction in the 6 years Ive been coding.Honored ContributorThank you tricky
