AHDL to VHDL

Synthesize them in Quartus and write out a VHDL/Verilog simulation file(Assignments -> Settings -> EDA). By default it runs after fit, but I think you can run it after synthesis only. The added benefit is you're actually simulating what Quartus synthesizes it too, not what something like XPORT sees. The downside is that you loose a lot of internal combinatorial names that get absorbed into LUTs, plus it's an additional step each time. (Although I'm guessing it runs pretty quick...)