Forum Discussion

HongLiang's avatar
HongLiang
Icon for New Contributor rankNew Contributor
3 years ago

Agilex DP IP integration with F-tile PHY some signals mismatch

We try to build a DP Rx function in Agilex. There are some DP RX interface need to connect to F-tile PHY IP we can not find them in the F-tile IP interface. We check the DP example...
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi Liang Hong,

Thank you for your feedback.

Since both forum cases reported by you are similar and pointing to same issue, I would like to suggest to only keep one case open as tracking to avoid miscommunication.

I have replied your forum case in Case No.05751620 , however I will put same reply below:

I have checked and generated a design example from my end and I do not observe any error in compilation.

Allow me to share with you my design for you to test from your end.

Q1. Did you change any setting in the Design example?

Q2. Do you mind sharing the steps/procedure that you use to generate the design example?

Thank you.

Best Regards,

ZulsyafiqH_Intel