Agilex DP IP integration with F-tile PHY some signals mismatch

Hi Liang Hong,

Apologize for the delayed response.

At the moment, for Agilex device, we have only 2 available design as below:

DisplayPort Intel FPGA IP Design Example for Intel Agilex F-tile Device

However, we do have a documentation from another device that you can use as reference to create DP RX design, you may refer to below link for more information:

AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design - 1.5. Creating the RX-only Design

I would like to clarify some information below:

Q1. Did you generate your design from design example?

Q2. Did you manage to compile the design? Any errors message or violation?

Q3. Could you share with us your .qar file?

Thank you.

Best Regards,

ZulsyafiqH_Intel