'after' in Timing Simulation tool

I'm create a simple program that simply delays the clock in 10ns.

I used:

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LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.ALL;

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ENTITY delay_clock IS

PORT ( clk : IN BIT;

clk_no_delay : OUT BIT;

clk_delay : OUT BIT);

END delay_clock;

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ARCHITECTURE test OF delay_clock IS

BEGIN

clk_no_delay <= clk;

clk_delay <= clk after 10ns;

--clk_delay <= '1';

END test;

But, when I simulate this in Quartus, the delay isn't 10 ns, why ???

Thank you,

Rester