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Altera_Forum
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17 years ago

ADPLL using Verilog? Not working!

Guys I am trying to implement ADPLL in verilog using Quartus-II so I can synthesis my model to an FPGA. on the internet (http://www-unix.ecs.umass.edu/%7edjasinsk/adpll.html) I have found this ...
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Altera_Forum
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17 years ago

The feasibility of an alternative method depends on the maximum sampling frequency that you can apply to the input data. The more you oversample the input, the more you will be accurate in clock and data recovery. But certainly, as FvM says, it is difficult to suggest you an appropriate solution without knowing well your application.