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Altera_Forum
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17 years ago

ADPLL using Verilog? Not working!

Guys I am trying to implement ADPLL in verilog using Quartus-II so I can synthesis my model to an FPGA. on the internet (http://www-unix.ecs.umass.edu/%7edjasinsk/adpll.html) I have found this ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Why are you using Verilog and not the PLL Megafunction of QuartusII?

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I need to synthesis my code on FPGA to test, then synthesized it an actual chip using CAD tools.. thats why..