Altera_Forum
Honored Contributor
Honored ContributorADPLL using Verilog? Not working!
Guys I am trying to implement ADPLL in verilog using Quartus-II so I can synthesis my model to an FPGA. on the internet (http://www-unix.ecs.umass.edu/%7edjasinsk/adpll.html) I have found this ...
