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Altera_Forum
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17 years ago

ADPLL using Verilog? Not working!

Guys I am trying to implement ADPLL in verilog using Quartus-II so I can synthesis my model to an FPGA. on the internet (http://www-unix.ecs.umass.edu/%7edjasinsk/adpll.html) I have found this ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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I see some dubious constructs, e. g. CK is a gated clock that probably has glitches and must cause timing violations. The code has to be reworked to get a proper synchronous design. Other issues may exist, too.

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Can u elaborate more please?