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Altera_Forum
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17 years ago

ADPLL using Verilog? Not working!

Guys I am trying to implement ADPLL in verilog using Quartus-II so I can synthesis my model to an FPGA. on the internet (http://www-unix.ecs.umass.edu/%7edjasinsk/adpll.html) I have found this ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Before looking though the code I thought I'd check the simple stuff first :)

What are you using for stimulus? Have you written a testbench? What drives the clock and reset inputs? (Looks like an active low reset)

Are you simulating on Quartus or modelsim?

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Im using QuartusII.

If u check the link in the first post wer I got the code from, it has figures for the block diagram and the supposed simulation results.