Adjustable frequency generator

I already changed that and it still doesn't work.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity     DIVIDER_2 is
port( 
clk:      in STD_LOGIC;
O     :      out STD_LOGIC 
);
end DIVIDER_2;
    
architecture DIVIDER_2 of DIVIDER_2 is    
    
    
    signal OI : STD_LOGIC;
    signal divider: integer range 0 to 20000:=666;        -- set divider
    signal counter: integer range 0 to 20000:=0;
    
    begin
    O <= OI;
    
    process (clk) is  
    
        begin
        if rising_edge (clk) then
        
            if (counter < divider) then
            counter <= counter + 1;
            else
            OI <= not OI;
            counter <= 0;
            divider <= divider + 1;
            end if;
        
        end if;
    
    end process;
end DIVIDER_2;