Adjacent PLL input

Moin

For flexibility reasons, I currently chain two PLLs on a Stratix III. The first one only drives the second one, fan-out is 1.

According to the device datasheet, there is the possibility to use an adjacent PLL output as clock input. But in my case, Quartus keeps using a global clock net for the connection between the two PLLs (how was that with saving resources?...).

Does anyone know if there is a way to specify this (besides trying to instantiate stratixiii_pll directly)? Or do I need to follow some rules in RTL to make this possible?

Thanks and best regards,

emanuel