adder is not packed into a DSP block in 1ST280EY2F55E2LGS1 FPGA.

Hi,

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.

Regards,

Nooraini

Hi,

Sorry for the delay. As I understand it, you encounter issue with DSP block packing when using a code template in S10 devices. By the way, I notice there is a similar request through IPS case 397623. Not sure if it is similar to this.

For your information, to allow the Fitter to pack into the DSP block correctly, you may do the one of the following:

1. Use the DSP Native IPs which you observe no issue with the DSP packing

2. Refer to the template which falls under:

Quartus -> Insert Templates -> Languague templates -> Verilog HDL -> Full Designs -> Arithmetic -> DSP Features -> DSP Features for 14-nm Device

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I have tested running compilation with one of the template from the above and does not observe any warning on packing.

Please let me know if there is any concern. Thank you very much.

Best regards,

Chee Pin