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SShiv1's avatar
SShiv1
Icon for New Contributor rankNew Contributor
7 years ago

adder is not packed into a DSP block in 1ST280EY2F55E2LGS1 FPGA.

I am using quartus18.1 dsp multiplier adder code template. adder is not packed into a DSP block in 1ST280EY2F55E2LGS1 FPGA. could you please send me the correct template.
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi,

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.

Regards,

Nooraini