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Altera_Forum's avatar
Altera_Forum
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12 years ago

Add test bench to project at modelsim

Hi , i create new project at modelsim and wrote hdl design and there aren't errors . i create test bench file at VHDL and i need to add the file to the project and compile the test bench , H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks a lot bertulus ,

i didn't know that i need to give an initial value to Reset , i assumed that it has '1' and after 10 nsec it goes to '0' like i defined it .

any way it works great now :) now i'm writing the Receiver Block that supposed to lock on the PRBS data (serial_out) .

Thanks a lot on the support !