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Altera_Forum's avatar
Altera_Forum
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12 years ago

Add test bench to project at modelsim

Hi , i create new project at modelsim and wrote hdl design and there aren't errors . i create test bench file at VHDL and i need to add the file to the project and compile the test bench , H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I found the problem. In the testbench you define the reset signal:

signal ResetN : std_logic;

but doesn't have an initial value, so modify it:

signal ResetN : std_logic := '1';

The circuit didn't receive a reset so the ff outputs had an undefined value.

When you simulate you have to stop it manually. You use a assert false directive to stop it when it reaches a special condition.