Add test bench to project at modelsim

Hi ,

i added the Test Bench to the project and compile the project at Quartos and at Model Sim and it passes successfully without errors .

i simulate the Test Bench and look at the waves , the clock and Reset of the Test Bench are shown o.k but the output data of

the project (serial data) is undefined ( shown as U ) .

i investigate the issue and create Test Bench for the lowest component and it works perfect - the serial data shown (attached at file) .

The 2 upper component only instantiate the port to the internal ports of internal component without any design .

what can you recommend me to do more regarding this issue ?