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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Add test bench to project at modelsim

Hi , i create new project at modelsim and wrote hdl design and there aren't errors . i create test bench file at VHDL and i need to add the file to the project and compile the test bench , H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If its a modelsim project, you can just add the testbench file to the project like any other VHDL file.

Or just compile it:

vcom my_testbench.vhd