Add subtract seven segments display

Hi

Dont worry - no question or code is too basic, we all had to start somewhere.

First off - I hope you werent told that Verilog is a programming language - it is nothing of the sort - it is a hardware description language. Thinking of it as a programming langauge will cause you problems.

Seconly, ISE is a Xilinx software suite and this is an Altera forum. While people can help with the HDL, they are unlikely to know much about how to use ISE. I suggest the Xilinx forum instead for these questions.

thirdly, you havent actually posted what problems you are having. Just posting the code and asking for help without specific questions is unlikely to receive a response.

So my questions : have you written a testbench? have you tried simulating your code?