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Altera_Forum
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13 years ago

ADC combining DDR channels

I have an ADC that is inputting data serially to the FPGA with a frame clock at 50MHz on two channels. On one channel the sample is complete on the rising edge of the frame clock, the other channel ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Ok, that is good enough for me then. I guess I was over thinking the issue and thought that the clock skew could be enough to disrupt the timing of the register.