A/D converter-FPGA-USB

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What is the relation between clock and data rate of digital device(e.g. ADC in my case)??

The ADC of daughter card support up to 65 MSPS(mega sample per second). Does it mean that we can use clock frequency less than 65 MHZ(lets say 50 MHZ or 2 MHZ) but can't use clock frequency greater than 65 MHZ (lets say 100 MHZ) to get output??

I used frequency 100 MHz from its oscillator and didn't get any output.

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A "65MHz ADC" can be clocked at up to 65MHz. 100MHz is too high. You can also clock it at lower frequency.

Cheers,

Dave

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I am using ADA_HSMC instead of GPIO as my daughter card only support HSMC.

Although using HSMC it doesn't make any difference to GPIO while capturing signal with Signal Tap if pin is mapped for HSMC instead of GPIO. Isn't it??

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As far as the FPGA is concerned, the two interfaces are the same; they connect to pins on the FPGA.

You can use SignalTap in both cases.

Cheers,

Dave

Hi, thanks for the reply.

So, can we say that ADC having maximum datarate 65 MSPS(mega sample per second) means it indirectly saying maximum frequency that it can support(here 65 MHZ)?

i.e. Data rate corresponds to frequency it supports. am i right??

and sorry if my question is so obvious.

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So, can we say that ADC having maximum datarate 65 MSPS(mega sample per second) means it indirectly saying maximum frequency that it can support(here 65 MHZ)?

i.e. Data rate corresponds to frequency it supports. am i right??

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There's several terms you need to use when thinking about ADCs

1) Sampling rate

This is the rate at which the analog signal is sampled. It is also typically the same as the clock rate. However, some devices have internal PLLs that define the clock rate, and so the external clock rate is not the same as the sample rate.

2) Data rate

Some ADCs output data at the same rate as their sample rate. Higher frequency parts include demultiplexing, so output wider data buses at a lower rate than the sample rate. Other ADCs multiplex the samples onto serial data streams (JEDEC JESD204) so the output data rate is higher than the clock rate.

3) Analog bandwidth

Many ADCs are used for sampling a band of frequencies. That band of frequencies can lie in a Nyquist zone, where a zone is a band with bandwidth of under fs/2. For example, the first Nyquist zone is at DC to fs/2, the second is fs/2 to fs, and the third is fs to 3fs/2. These types of ADCs are called IF sampling or direct conversion ADCs. They save you a downconversion by using aliasing to get the signal to baseband.

Read the data sheet for your ADC board and the data sheet for the ADC IC on the board, and you'll find these terms, or terms very similar to this.

Cheers,

Dave

What have you setup for the clock source?

Page 2 of the schematic has the ADC. There is a POWERON signal, and ADC_CLKA and ADC_CLKB clocks. Have you got something driving those signals?

The ADC_CLKA and ADC_CLKB signals come from the headers JP1 and JP2. Which jumper do you have attached?

Do you have an input signal attached? If you do not, then the ADC will sample whatever the center tap value is. Assuming the ADC outputs in 2's compliment format, that could be zero (0) or all ones (-1).

Cheers,

Dave

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What have you setup for the clock source?

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I tried in following 2 ways and none of them worked:

1. using the 100 MHZ oscillator of daughter card by setting jumper between 3 & 4 of JP1 as given in schematic.

2. using the oscilltor of FPGA board having 50 MHZ and map this signal with ADC_CLK_A as a PLL. and in this case setting jumper between 1 & 2 of JP1 as given in schematic.

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Page 2 of the schematic has the ADC. There is a POWERON signal, and ADC_CLKA and ADC_CLKB clocks. Have you got something driving those signals?

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I didn't find any setting for POWERON signal. For ADC_CLK_A, I used as described above in 1 & 2.

For ADC_CLK_B: As i am using only one channel (Channel A), So, I think it will not be necessary.

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The ADC_CLKA and ADC_CLKB signals come from the headers JP1 and JP2. Which jumper do you have attached?

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JP1 setting is described above and JP2 setting I don't need it as I am using only one channel (channel A).

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Do you have an input signal attached? If you do not, then the ADC will sample whatever the center tap value is. Assuming the ADC outputs in 2's compliment format, that could be zero (0) or all ones (-1).

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yes, I have attached the input signal.

I guess I also have to set some control signals for these two:: "I2C for HSMC" (I2C_SCLK and I2C_SDAT) but not sure.

If you have an oscilloscope, probe the HSMC connector pin and check that you can see a clock there. Alternatively, use SignalTapII - you don't have to use a synchronous clock for this, just use whatever clock is on the DE board to capture the clock pin from the HSMC board. If you do not see toggling, then you are not getting a clock with your data.

Read the data sheet to see what to do with the POWERON signal ... from its name I suspect you need to use it :) Probe the board and see if it is at the correct level to enable the ADC channel.

Cheers,

Dave

Hi, thanks for your valuable suggestion.

Now, I got the ADC output. I can see the output in Signal Tap analyser for individually 14 bits and also as a whole for all 14 bits in the hex form. For clarification, I attached the file here. even output also see on the led using counter.

using "create signal Tap II list file", I have also created one text file. but unfortunately this file is only for 128 samples (from -16 to +111) and unable to ctreate such file for more samples.

Is it possible to create such file for lets say thousands of samples??

Is it also possible to capture single waveform(not just as hex format) instead of individual 14 bits, same like analog signal so that further processing will be easy??.

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Now, I got the ADC output. I can see the output in Signal Tap analyser for individually 14 bits and also as a whole for all 14 bits in the hex form. For clarification, I attached the file here. even output also see on the led using counter.

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Great! It looks like all bits are toggling.

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using "create signal Tap II list file", I have also created one text file. but unfortunately this file is only for 128 samples (from -16 to +111) and unable to ctreate such file for more samples.

Is it possible to create such file for lets say thousands of samples??

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If you click on the Setup tab in SignalTap II, on the right is the sample depth. You can select the number of samples to capture there.

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Is it also possible to capture single waveform(not just as hex format) instead of individual 14 bits, same like analog signal so that further processing will be easy??.

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I believe the data captured by SignalTap II can be read using external tools. However, I've never had to use that feature.

When I want to capture a block of samples from an ADC, I'll typically write my own code to capture to a RAM block or multiple RAM blocks. The RAMs are configured as dual-ported, with one side connected to the ADC, and the other connected to an Avalon-MM system. I then read the captured samples from RAM using the JTAG interface, via the method described in this tutorial

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

Cheers,

Dave

Hi, As output from 14 bit ADC is in 2's complement form having 1 volt reference voltage. and I am trying to convert it into Sign Magnitude in following way:

process (CLOCK_50)

begin

if rising_edge(CLOCK_50) then

if (ADC_DA(13)='1') then --for -ve value

calculation<=ADC_DA-1;

calculation<=NOT(calculation);

calculation(13)<= '1';

LEDR <= calculation;

else

LEDR<=ADC_DA; --for +ve value

end if;

end if;

end process;

but not getting desired output in signal tap anyser for LEDR here.

Am I missing something??