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What have you setup for the clock source?
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I tried in following 2 ways and none of them worked:
1. using the 100 MHZ oscillator of daughter card by setting jumper between 3 & 4 of JP1 as given in schematic.
2. using the oscilltor of FPGA board having 50 MHZ and map this signal with ADC_CLK_A as a PLL. and in this case setting jumper between 1 & 2 of JP1 as given in schematic.
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Page 2 of the schematic has the ADC. There is a POWERON signal, and ADC_CLKA and ADC_CLKB clocks. Have you got something driving those signals?
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I didn't find any setting for POWERON signal. For ADC_CLK_A, I used as described above in 1 & 2.
For ADC_CLK_B: As i am using only one channel (Channel A), So, I think it will not be necessary.
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The ADC_CLKA and ADC_CLKB signals come from the headers JP1 and JP2. Which jumper do you have attached?
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JP1 setting is described above and JP2 setting I don't need it as I am using only one channel (channel A).
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Do you have an input signal attached? If you do not, then the ADC will sample whatever the center tap value is. Assuming the ADC outputs in 2's compliment format, that could be zero (0) or all ones (-1).
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yes, I have attached the input signal.
I guess I also have to set some control signals for these two:: "I2C for HSMC" (I2C_SCLK and I2C_SDAT) but not sure.
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