--- Quote Start ---
Check if you possibly have a situation like the one I explained here in the second part of the message:
http://www.alteraforum.com/forum/showthread.php?t=37697 In any case, I suggest you add in the new design a blinking LED, a switching signal or anything else in order to make sure fpga has been correctly configured.
--- Quote End ---
Thank you Cris72. I have seen your the other post as followed.
"
I often observed this behaviour in two situations:
The first one happens when I first load a design, then I load a different one without closing the previous Nios console window. Although this seems not to be your case, all I need to do here is closing the old window.
The second one is more subtle: it happens when I saved the previous design in a NV memory (epcs or whatever) for automatic boot upon power up. If you then load with jtag a newer design having the same base epcs address, the OLD Nios firmware would indeed boot from epcs and this could lead to the inconsistency error. The solution is making sure epcs is blank when you switch to a new design.
"
But i am sorry i have not understand what your say. Could you give me more explaination?
I have try lots of approach, for example to build a new Nios system after remove the legacy one, check the jic file, sof file and elf file is for one project. I also observe other solution posted in this forum. But there is no any good news.
Honored Contributor
