Active-HDL Disable SystemVerilog

Hello,

Is it possible to disable SystemVerilog assertion module within Active-HDL? The feature is not currently purchased by my company and I keep getting the following error.

# ELBREAD: Error: You do not have a valid license to simulate SystemVerilog assertion module 'rldram_example.genblk220'.# Contact Aldec for ordering information - sales@aldec.com.# ELBREAD: Error: Elaboration process completed with errors.