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Altera_Forum
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9 years ago

Achieving higher data-rates on Cyclone V pins - Balancing internal routing delays

Hello all,

I am looking for some help trying to close the timing for a new design.

I need to inferface a Cyclone V with an octal 14-Bit serial LVDS ADC running at 40 MSPS. The ADC digital output is synchronous DDR at 280MHz, that is, a serial stream of 560Mbps.

The problem is that some of the LVDS channels are assigned to dedicated pins for a Hard memory Controller, which introduce a greater delay, therefore reducing the maximum data-rate at which we can receive data. According to Cyclone V handbook, it is not recommended o use HMC pins for signals faster than 200MHz, but I would like to try to overcome this problem.

One option I found was to tune the phase shift of the internal clock used to sample data with a PLL so that I could sample the incoming stream from all the 8 channels at the cost of not sampling it right in the middle. However, I do not have PLLs available to do this phase shift in the design and I have discarded this option.

The second option I considered is to introduce a certain delay in all the lines that are not assigned to a Hard memory controller pin, so that the delay gets compensated in all the channels and I can sample it one clock cycle later.

I have been trying to achieve such a delay by means of timing constraints, as the forum member Rysc explained in posts http://www.alteraforum.com/forum/showthread.php?t=3028 and http://www.alteraforum.com/forum/showthread.php?t=3068, but I have been not able to get a fine enough tuning of such delays, furthermore, the results I get are sometimes completely wrong, with delays far beyond the values I specified.

For instance, for an internal path between two FF where I want to have a minimum delay of 2.5ns and a maximum delay of 3ns, the delays I get are over 4-5ns :-(

Do you think it is feasible to find such a solution? And if so, do you see any drawbacks? Perhaps there is another way to tell Quartus to balance the delay of all the lines, at some point I thought it would do it itself automatically. Frankly, I have not seen such a solution before, maybe its too exotic, but I think that the additional delay of Hard memory controller pins should not be a limiting point to work at high data-rates.

Thanks a lot for your help!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi again,

    Let me bring up this post to see if someone has anything to comment, I find this topic might be interesting.

    Summarizing my previous (loooong) post, in Cyclone V FPGAs with Hard Memory Controllers (HMC), Altera recommends not to use dedicated HMC pins for signals faster than 200MHz. The reason behind it is that these pins are routed through routing elements (HMCPHY_RE) that introduce a higher delay compared to the other non-dedicated pins. I have checked this fact with TQ tiiming analyzer, and indeed the delay introduced by these routing elements is higher, about 2-3ns relative to other I/O pins.

    My point here is that a a longer delay should not be a problem to work at higher data-rates than those 200Mbps as long as the delay is balanced among all the inputs. What do you think of this assumption?

    Then, the final goal of all this is to find a way to tell Quartus to balance these delays between dedicated and non-dedicated pins for instance, by means of timing constraints.

    Do you have any comments?