Honored Contributor
Honored ContributorHi again,
Let me bring up this post to see if someone has anything to comment, I find this topic might be interesting. Summarizing my previous (loooong) post, in Cyclone V FPGAs with Hard Memory Controllers (HMC), Altera recommends not to use dedicated HMC pins for signals faster than 200MHz. The reason behind it is that these pins are routed through routing elements (HMCPHY_RE) that introduce a higher delay compared to the other non-dedicated pins. I have checked this fact with TQ tiiming analyzer, and indeed the delay introduced by these routing elements is higher, about 2-3ns relative to other I/O pins. My point here is that a a longer delay should not be a problem to work at higher data-rates than those 200Mbps as long as the delay is balanced among all the inputs. What do you think of this assumption? Then, the final goal of all this is to find a way to tell Quartus to balance these delays between dedicated and non-dedicated pins for instance, by means of timing constraints. Do you have any comments?
