Altera_ForumHonored Contributor12 years agoAccessing SDRAM memory on Terasic DE0-Nano board. I want to use SDRAM memory located on DE0-Nano board using Verilog (without using Nios). I use http://www.altera.com/support/examples/nios2/exm-avalon-mm.html System placed in the QSYS: htt...Show Moreqsys.jpg300 KB
Altera_ForumHonored Contributor12 years agoProblem fixed. Need to wait two clock tacts before reading.
Recent DiscussionsHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorConnection bit order between hierarchyCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: