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Not sure what referencing a hierarchical name inside the current module would be. Doesn't sound like hierarchy to me.
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In deed. I found, that you're allowed to prefix a module internal item with it's module name without causing a syntax error. But it's of course meaningless.
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I wonder how Altera does it with the SignalTap II Logic analyzer?
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Hierarchical names exist of course inside the design (in a AHDL or whatever syntax), but you don't necessarily have a high level (VHDL/Verilog) interface. Finding the exact internal item name can be even less comfortable then routing the signal through the hierarchies, I fear. You also have these problems in SignaTap II: A signal, that appears in the node browser is not necessarily accessible in the same module.
Supporting the well-defined hierarchical names mechanism of Verilog (my favourite VHDL unfortunately hasn't it) would be an actual high level approach. In VHDL, I have the option to use a structured inout signal as a debug "bus", that can be connected where needed. It possibly works with a bit vector in Verilog as well.
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