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Altera_Forum's avatar
Altera_Forum
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16 years ago

accessing internal nodes

In verilog, I am trying to connect to internal nodes from the top level of a design for debug. The debug module is a serial input DAC control module that is used to look at internal nodes using an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi GPK

I looked into signal probe, but didn't have too much luck. It seems the destination wants to be a pin, and I need it to be a port to another module. I need to connect to a module that serializes the data for the external DAC.

Tricky...I'll give the assignment editor a try, maybe some type of ECO.

I wounder how Altera does it with the SignalTap II Logic analyzer?

Thanks for you help,

Lindy

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Hi Lindy,

I think I misundertand you. I though that you would like to see the internal signal directly on device pins, in order to measure the signals with e.g. a scope. It seems to me that you want to connect an additional block to internal signals of your design and the block is on the toplevel , right ?

Kind regards

GPK