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I need to see the internal signals in relation to other analog external signals. I don't know of a way to do this with Signal tap. I don't have an extra external DAC to bring the signals into the FPGA.
I did find out that Quartus doesn't support hierarchical names out side the current module. Not sure what referencing a hierarchical name inside the current module would be. Doesn't sound like hierarchy to me.
I started updating my code with `ifdef & `endif to route the signals up at compile time. What a mess.
I did see there is a tcl command called make_ape_connection that belongs to the chip_planner. I was thinking I could instantiate the modules an then hook the connections up with this this command. Has anyone done something like this?
Thanks,
Lindy
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Hi Lindy,
did you give signalprobe a try ? Is it not usable for you ?
Kind regards
GPK
Honored Contributor
