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In verilog, I am trying to connect to internal nodes from the top level of a design for debug. The debug module is a serial input DAC control module that is used to look at internal nodes using an oscilloscope. It would be very painful to bring all the nodes I would like to look up through the hierarchy to a single location. I have simulated something similar with cadence ncsim before without an issue… I do believe the internal node needed to be a wire. Is there a way to do this in Quartus?
This is in the top module: hierTest
sysLogic I1 (
.IN(DATA[7:0]),
.CLK(CLK),
.RESET(RESET));
dacCtl I2 (
.IN(I1.I2.OUT[7:0]), // I1.I1.OUT[7:0] is the output a registers in I1.I1, Also tried a wire
.LD(I1.I2.LD),
.SDO(SDO)
.SCK(SCK),
.SLD(SLD),
.CLK(CLK),
.RESET(RESET));
Error (10207): Verilog HDL error at hierTest.v(31): can't resolve reference to object "OUT"
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Hi,
why don't you use Signaltap ?
Kind regards
GPK
Honored Contributor
