Accessing individual nodes in a bus

Tricky

I think I got going in the direction I want if there is not a better way https://www.alteraforum.com/forum/attachment.php?attachmentid=12012 by modifying the symbol file by adding q_0 unless there is a better way

Roger50310

ENTITY CntMod4 IS

PORT

(

clock : IN STD_LOGIC ;

cnt_en : IN STD_LOGIC ;

q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);

q_0 : OUT STD_LOGIC

);

END CntMod4;

ARCHITECTURE SYN OF cntmod4 IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0);

COMPONENT lpm_counter

GENERIC (

lpm_direction : STRING;

lpm_modulus : NATURAL;

lpm_port_updown : STRING;

lpm_type : STRING;

lpm_width : NATURAL

);

PORT (

clock : IN STD_LOGIC ;

cnt_en : IN STD_LOGIC ;

q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);

q_0 : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

q <= sub_wire0(2 DOWNTO 0);

LPM_COUNTER_component : LPM_COUNTER

GENERIC MAP (

lpm_direction => "UP",

lpm_modulus => 4,

lpm_port_updown => "PORT_UNUSED",

lpm_type => "LPM_COUNTER",

lpm_width => 3

)

PORT MAP (

clock => clock,

cnt_en => cnt_en,

q => sub_wire0,

Q_0 => sub_wire0(0)

);