Occasional ContributorAbout Virtual Clocks in Constraints
It would be helpful if you could teach us the following points about virtual clocks.
1) The timing analyzer user guide states that it is used to limit the data output from the FPGA to the external device, but is that understanding correct?
2) If you search on the web, you will find an article stating that a virtual clock is specified when restricting I/O regardless of input/output. Should I use a virtual clock for I/O constraints even if the design receives data on that clock?
Sorry for the elementary question, but it would be helpful if you could teach me.
Virtual clocks represent the clocks that drive external devices, those that drive into the FPGA on inputs (upstream) and those that drive devices fed by the FPGA on outputs (downstream). I'm not sure what you mean by "limit the data output from the FPGA to the external clock." On outputs, the virtual clock is used as the latch clock and the setup and hold timing requirements at the downstream device are based off of it. On inputs, the virtual clock acts as the launch clock and the tco of the upstream device is based off of it.
For synchronous I/O timing analysis, the virtual clock is always the clock that is referenced when creating your set_input_delay and set_output_delay constraints so even if the same physical clock drives both the external device and the FPGA, you should always create a separate virtual clock with create_clock. Virtual clocks are created with create_clock by not specifying a target (but including a name), something like:
create_clock -name virt_clock -period 10
