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Altera_Forum
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13 years ago

about vhdl code for cic interpolation filter

i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic inter...
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Altera_Forum
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12 years ago

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you need sign extend:

data_24 <= std_logic_vector(resize(signed(data_23)),24) + resize(signed(data_23b)),24);

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I have not understood clearly what data_24,std_logic_vector(resize(signed(data_23)),24),resize(signed(data_23b)),24) stands for.especially what does signed(data_23b)),24 stands for .can you explain me properly?