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Thanks FvM.
I assume the equations for bit growth given in attached doc look too involved to be wrongly typed from original source(Hogenauer's).
But I did notice discrepancy of last equation when applied to i = N as Bout = Bin + N -1
Anyway do you have access to Hogenauer's doc? or do you know where those given equations go wrong.
I know Hogenauer also included method for register pruning to reduce bit growth by distributing quantisation noise across stages. Naturally too involved and too specialised corner and may be unwarranted with FPGAs applications.
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i am attaching that Hogenauer's doc.but still i am not able to solve the overflow problem in the integrator with the output width as obtained
Bin = 24;
%input width
N = 9;
%stages of comb or integrator
M = 1;
%differential delay
R = 8;
%interpolation rate
%cic decimator at any stage
Bout = N * log2(R*M) + Bin;
%cic interpolator per ith stage
%stages 1~N
for i = 1:N
G = 2^i;
Bout = Bin + log2(G);
d(i) = Bout;
end
%N+1 ~ 2N stages
for i = N+1:N*2
G = 2^(2*N-1)*(R*M)^(i-N)/R;
Bout = Bin + log2(G) - i + 1;
d(i) = Bout;
end
for
i = 1:N*2
fprintf(
'%i %i\r',i,d(i));
end
the d output obtained is as follows
1 25
2 26
3 27
4 28
5 29
6 30
7 31
8 32
9 33
10 32
11 34
12 36
13 38
14 40
15 42
16 44
17 46
18 48
especially at the 9th stage of the comb section the output width is 33 and the interpolating factor is 8 .The input to first stage of integrator is 33 bit width and the output of second stage of integrator is 34.But still there is qverflow problem in the second integrator stage.Why that problem is coming can you explain it the reason?
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