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After further work it turned out that my last statement needs correction.
The best thing is run this matlab program and read (d):
Bin = 23; %input width
N = 9; %stages of comb or integrator
M = 1; %differential delay
R = 8; %interpolation rate
%cic decimator at any stage
Bout = N * log2(R*M) + Bin;
%cic interpolator per ith stage
%stages 1~N
for i = 1:N
G = 2^i;
Bout = Bin + log2(G);
d(i) = Bout;
end
%N+1 ~ 2N stages
for i = N+1:N*2
G = (2^(2*N-1)*(R*M)^(i-N))/R;
Bout = Bin + log2(G);
d(i) = Bout;
end
for i = 1:N*2
fprintf('%i %i\r',i,d(i));
end
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after checking the matlab code above the value of d is as below
1 24
2 25
3 26
4 27
5 28
6 29
7 30
8 31
9 32
10 40
11 43
12 46
13 49
14 52
15 55
16 58
17 61
18 64
Now my question is with 23 bit input data how to write vhdl code so that the ouput data width is 24 and follows.Since addition of 2 23 bit input data as shown in the comb section of the cic interpolation is 23 bit data and if i specify output data widthto be 24 there will be syntax error while synthesizing the vhdl code that datatypes are not matching.Can you give solution for this problem?
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