About VGA Output

Hello,

I am working for the first time with FPGA (cyclone v soc) and i am trying to get a output from VGA Port on the monitor. I have set the resolution for 1024x768 and PLL input frequency as 50MHz and output frequency as 65MHz as required for the resolution.But as soon as i program the board the monitor is going to sleep mode. I am attaching the code which i used for this. Can you please tell me what may be the problem. When I checked in RTL Simulation PLL is not generating any clock output.

Thank you in advance.

Code:

----Main code

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;

ENTITY VGA IS

PORT(

CLOCK_24: IN STD_LOGIC;

SYS_rst : IN STD_LOGIC;

VGA_HS, VGA_VS: OUT STD_LOGIC;

VGA_R, VGA_G, VGA_B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

VGA_CLK_65MHZ : OUT STD_LOGIC

);

END VGA;

ARCHITECTURE MAIN OF VGA IS

SIGNAL VGACLK, RESET, lock : STD_LOGIC :='0';

signal SIGNAL_135MHZ : STD_LOGIC:= '0';

COMPONENT SYNC IS

PORT

(

CLK : IN STD_LOGIC;

HSYNC, VSYNC : out std_logic;

R, G, B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END COMPONENT;

component unsaved is -- PLL Component

port (

pll_0_locked_export : out std_logic; -- pll_0_locked.export

pll_0_outclk0_clk : out std_logic; -- clk

pll_0_refclk_clk : in std_logic := '0'; -- clk

pll_0_reset_reset : in std_logic := '0' -- reset

);

end component unsaved;

BEGIN

inst_pll : UNSAVED port map

(

pll_0_refclk_clk => clock_24,

pll_0_reset_reset => SYS_rst,

pll_0_outclk0_clk => VGACLK, ---CLOCK 65 MHZ

--outclk_1 => SIGNAL_135MHZ, --- CLOCK 135 MHZ

pll_0_locked_export => lock

);

INST_SYNC : SYNC PORT MAP

(

CLK => VGACLK,

HSYNC => VGA_HS,

VSYNC => VGA_VS,

R => VGA_R,

G => VGA_G,

B => VGA_B

);

VGA_CLK_65MHZ <= VGACLK;

END MAIN;

---Sub Program

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;

ENTITY SYNC IS

PORT(

CLK : IN STD_LOGIC;

HSYNC, VSYNC : out std_logic;

R, G, B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END SYNC;

ARCHITECTURE MAIN OF SYNC IS

SIGNAL HPOS: INTEGER RANGE 0 TO 1344:=0;

SIGNAL VPOS: INTEGER RANGE 0 TO 806:=0;

BEGIN

PROCESS(CLK,HPOS,VPOS)

BEGIN

IF(CLK' EVENT AND CLK='1') THEN

IF (HPOS = 832 OR VPOS = 422) THEN

R <= (OTHERS => '1');

G <= (OTHERS => '1');

B <= (OTHERS => '1');

ELSE

R <= (OTHERS => '0');

G <= (OTHERS => '0');

B <= (OTHERS => '0');

END IF;

IF(HPOS<1344) THEN

HPOS <= HPOS+1;

ELSE

HPOS <=0;

END IF;

IF (VPOS<806)THEN

VPOS <= VPOS+1;

ELSE

VPOS <=0;

END IF;

END IF;

IF (HPOS > 24 AND HPOS < 160)THEN

HSYNC <= '0';

ELSE

HSYNC <= '1';

END IF;

IF (VPOS > 3 AND VPOS < 9) THEN

VSYNC <= '0';

ELSE

VSYNC <= '1';

END IF;

IF ((HPOS> 0 AND HPOS< 320) OR (VPOS>0 AND VPOS< 38)) THEN

R <= (OTHERS => '0');

G <= (OTHERS => '0');

B <= (OTHERS => '0');

END IF;

END PROCESS;

END MAIN;