pnayak15 -
Ok, now we're getting somewhere. It sounds like you have an Altera dev kit. And when you power up the board the dev kit displays the Altera logo on the monitor. Do you have the source code for the FPGA design that came with the board? Normally that is provided with a dev kit. If you have that then look at it and see what's different from what you're doing, especially how sync is generated. The ADV7123 does not take VSYNC and HSYNC, which is what you are generating. It needs composite sync, which is basically VSYNC and HSYNC combined into one signal, with a few specific differences. Once you drive SYNC/ correctly you should get an image. And you'll also need to drive the BLANK/ signal high.
Good luck, you're getting close!
Bob