Contributor
Super ContributorWhat device are you using? Is this a hardened EMIF or soft? Yes, the placement of pins would have an effect on timing analysis. Make sure all of your constraints, including I/O pin locations, are created to get an accurate analysis.
ContributorHi sstrell,
Device : arria 10 , 10ax115s2f45i1sg
EMIF: hard controller & PHY
Pin placement: no placement constrains for all EMIF interfaces (make quartus II assignment automatically)
And I found that I make one ddr refclk constrains in my .sdc file though there is one ddr refclk constrains in the .sdc file which generated with EMIF IP generation, and there is timing violation; And if I don't make this clock constrains in my .sdc file, there is no timing violation apperence. I think this constrain conflicts with the content of the clock constraints in EMIF.
Brs,
Lambert
