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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

About Timing Constraints

It would be helpful if you could teach us about the following points with the "Set Input Delay" command. 　1) In the case of the maximum delay setting, does this mean that the delay value is fitted ...
  • sstrell's avatar
    sstrell
    3 years ago

    No, as mentioned, set_input/output_delay specifies external delays so the Fitter knows where to place input or output registers to meet timing on the inputs or timing at the downstream device on outputs. set_max/min_delay is a way of specifically saying to the Fitter "I want this path to have a max delay of x and a min delay of y." Both sets of commands affect how the Fitter places and routes things.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

As you may already know, the" set_input_delay" is a timing constraint, used to describe a circuit outside of the FPGA. (same as set_output_delay )


The target delay should be equal to the set value that you set, for both min and max setting.

The maximum input delay (-max) is used for clock setup checks or recovery checks and the minimum input delay (-min) is used for clock hold checks or removal checks.

As the -max value increases, the setup requirement gets tighter because the FPGA's internal delays must get smaller in order to meet the setup relationship between clocks.

Likewise, as the -min value decreases, the hold requirement gets tighter, because the FPGA must add more delay in order to meet the hold relationship between clocks.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683432/22-4/tcl_pkg_sdc_ver_1-5_cmd_set_input_delay.html


Here's a case scenario for better understanding:

Let's say I have a signal coming into the FPGA on port din, which goes through some combinatorial logic and out through dout. To constrain it, I might do something like:

create_clock -period 20.0 -name ext_clk

set_input_delay -clock ext_clk -max 4.0 [get_ports din]

set_output_delay -clock ext_clk -max 7.0 [get_ports dout]


(Note that I did not do -min delays. I am going to ignore hold time analysis for this example, but normally a design should have this too.)

Anyway, the set_input_delay and set_output_delay describe registers outside of the FPGA and states they are clocked by ext_clk.

As such, there is a default setup relationship of 20ns when this clock is the source and destination. This is the lowest priority.

Since 11ns of delay (4+7) are used externally, the FPGA must get its signal from din to dout in 9ns.


A user could then add a multicycles if that is too tight of a requirement:

set_multicycle_path -setup 2 -from [get_ports din] -to [get_ports dout]


This multicycles has priority over the default clock relationship, and makes the setup relationship two clock periods, or 40ns.

Since 11ns are used externally, the FPGA must get its data from din to dout in 29ns.


Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.