About timing constraints of ‘in2out’ timing path

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I'm sorry for the description fault, the tool calculate the required time is as follows:

2ns(max_delay) - 3ns(output_delay) = -1ns;

And the arrived time is as follows:

3ns(input_delay) + tDELAY;

So tools think the constraints should be:

3ns(input_delay) + tDELAY < -1ns => tDELAY <-4ns;

But my thinking is that I want to constraint the max delay time is 2ns from ina to oub (tDELAY < 2ns), so, for that, I need to constraint the max_delay is 8ns;

It is right?

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I don't see how you found out what the tool is thinking.

set_input_delay has nothing to do with tdelay path. It is meant for register path only, so is set_output_delay. And in both cases it has nothing to do with concept of pure delay.

set_input_delay is information to the tool about data/clock offset arriving at pins. set_output_delay is information to the tool about allowed range of data/clock offset ejected at output pin.

The path of tdelay is comb. from pin to pin and I suppose it will be dealt with independant of register path. Whether you get it or not is up to your luck but still I don't understand the merits of your approach from basic design perspective. May be you tell us what is the purpose of your constraints...